Design of a Low-Voltage Low-Power Amplifier Cell

for 16-bit Sigma-Delta Converter

Eng Wei Koo

In VLSI technology, higher-order Sigma-Delta modulators provide an effective means of high-resolution A/D conversion for signals of low to medium bandwidths. Due to the growing trend in technology and voltage scaling in VLSI technologies, analog cells soon become the bottleneck of high-performance Sigma-Delta modulators. In paticular the performance of many key parameters of the amplifier is reduced.
A low-voltage low-power fully differential two-stage Class A/AB amplifier is presented in this paper. Simulation results indicated that the DC gain of the designed amplifier is in excess of 69dB and the unity-gain bandwidth is 17.7MHz with phase margin of 72 degrees.
When operated from a 1.8V supply voltage, the power dissipation of the core amplifier is approximately 0.66mW.
Layout of the amplifier has been done to integrate the design into a 1.2um CMOS technology and is currently queued for fabrication at MOSIS

Complete thesis:
thesis.pdf

Conference Paper:
Conference_paper.pdf

Useful links:
MOSIS Web Site:    http://www.mosis.org/

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