The University of Queensland UQ NavigationUQ HomeUQ SearchUQ MapsUQ ContactsUQ FAQsUQ Library
ITEE Innovation Expo 2001
  World Class: Be Part of It

Innovation Expo 2001 Image

On this site

  Head of School's Welcome
  Mayne Hall Floorplan
  Programme
  Location
  Sponsors
  Student Project List
  Prizes
  Gallery
  Acknowledgements

Quick Links

  ITEE Innovation Expo 2001

  QR CSEE Innovation Expo 2000



  Home » Student Projects » s369230

USB as an IP Module for FPGA Designs

Student: Myilone Anandarajah

Supervisor: Dr. Adam Postula

Category: Computer Systems Engineering Thesis Project

Text Description of Image

The USB controller IP for FPGA designs provides an interface for “system on a chip” designers to connect to a USB bus. This will save them design time and the time required debugging and testing a USB Controller if they were to implement the functionality of the IP themselves. The controller IP provides much of the functionality of high end USB controllers. The IP has been developed in VHDL which is a widely used hardware description language and is supported by the major FPGA designers such as Xilinx and Altera. The VHDL code for the IP is synthesiseable onto a Xilinx Spartan XL FPGA and is synthesiseable into other types of FPGAs with minimal modification.

The electronic industries race to reduce the size of devices has led to the design of entire systems on a chip. The USB standard has made attaching peripherals to PCs incredibly simple. These trends of “System on a Chip” and the rising popularity of USB is the basis of this thesis.

Text Description of Image

 

 

Poster Presentation (PDF)

Thesis Document (PDF)

feedback
©2001 The University of Queensland, Australia
ABN: 63 942 912 684
Authorised by: Secretary & Registrar
Maintained by: webmasters@itee.uq.edu.au
  Last Updated: 2 July 2001