Design of an Native Embedded Java Processor

Student: Jeremy See Wei Chan

Supervisor: Dr. Adam Postula

Category: Computer Systems Engineering Thesis Project

In embedded systems, designers want more powerful tools to develop their products. There is a growing desire for threading and garbage collection and Java is becoming an attractive candidate to fill the void. One of the important stepping-stones is building the tools to facilitate Java’s progression into the embedded arena.

In this thesis, a Java native processor is developed on FPGA. A class linker and bootstrap programs are created to support execution of Java classes. Subsets of the instruction set were classified and selected based on their importance and difficulty for implementation on the processor. After a comparison of existing Java processors and their architectures, a non-pipelined multi-cycle data path was chosen to be prototyped largely due to time-constraints. Simulations were used to ensure correct functionality and synthesis results were used to reduce gate counts and optimise timing results. An in-circuit debugger was designed to assist in testing and co-simulation of the device against RTL and instruction simulator models.

Implementation results indicate that the design is stable at 24 MHz on a Xilinx Spartan II FPGA. A static class linker enabled the processor to run existing Java classes. The processor provides basic application support but requires further work in order to support, real-time garbage collection and threading.

Poster Presentation (PDF)

Thesis Document (PDF)

Other Related Files