The University of Queensland UQ NavigationUQ HomeUQ SearchUQ MapsUQ ContactsUQ FAQsUQ Library
ITEE Innovation Expo 2002
  World Class: Be Part of It



On this site

  Head of School's Welcome
  UQ Centre Floorplan
  Programme
  Location
  Sponsors
  Student Project List
  Prizes
  2001 Photo Gallery
  Contact Details

Quick Links

  ITEE Innovation Expo 2002
  ITEE Innovation Expo 2001


  Home » Student Projects » Jackie Chan

An ADSL Telecommunications Testbed: Hardware Aspects

Student: Jackie Chan

Supervisor: Vaughan Clarkson

Category: Engineering Thesis Project - Communications

Over the past few years, the use of Broadband ADSL technology has increased dramatically and become part of our everyday life. It is considered the next-generation wide-area network access technology capable of alleviating today's data transmission bottlenecks. Applications such as remote LAN access/telecommuting, distant learning, streaming video and multimedia access which were once very inefficient at slow speed, now comes into reality at an affordable rate. Although most people say that ADSL is the transition from existing copper lines to the future optic fiber cables, its significance should still not be neglected as many leading research groups are still putting their efforts into developing systems with better performance. Future developments in this technology could lead to much higher data rates. It seems like an endless competition in the telecommunications industry as people are always greed of faster network access technology.

The focus on this thesis is to document the design and implementation of a digital signal processing (DSP) testbed on which to test various algorithms associated with ADSL technology.

This thesis uses the TMS320C6711 DSP Starter Kit as a DSP platform to provide a powerful mechanism for all necessary data manipulations and calculations. The ADSL signals are actually coded and decoded using a specialised ADSL codec which is then interfaced with the DSP through the daughterboard interface provided. This codec is essentially an ADSL modem that is capable of transmitting and receiving analog signals on a small loopback configuration. On the daughterboard interface, the DSP provides a parallel, 32-bit data interface which is a very fast data transfer mechanism that allows exchange of data with the codec. All the control signals are then accessed by the codec through the Multichannel Buffered Serial Port on the DSP.

 

 

Thesis Document (PDF)

feedback
©2001 The University of Queensland, Australia
ABN: 63 942 912 684
Authorised by: Secretary & Registrar
Maintained by: webmasters@itee.uq.edu.au
  Last Updated: 2 July 2001