JPEG2000 Coprocessing

Student: John Ruberry

Supervisor: Peter Sutton

Category: Engineering Thesis Project - Electrical

This thesis continues the work begun by James Brennan in his 2001 thesis, FPGA Coprocessing in a JPEG2000 Implementation. Brennan wrote and simulated VHDL code for the arithmetic encoder module of the JPEG2000 algorithm but did not implement it on the Annapolis WILDCARD PC card as he had planned.

JPEG2000 is the most recent image coding system developed by the Joint Photographic Experts Group (JPEG). It is intended to supersede the original JPEG standard in many applications, including digital cameras, the Internet and scanning equipment. In particular there has been much interest in applying the standard to satellite photography.

It was hoped that this project would produce a working implementation of Brennan’s arithmetic encoder on an FPGA, give a timing analysis for this implementation and offer an improvement in maximum clocking frequency. The goal of implementing Brennan’s code was not met but the maximum clocking frequency was successfully increased from 54.9MHz to 56.8Mhz by the addition of pipelining stages before the main registers in the encoder. It is estimated that this would represent a little over a 2.5% time saving in a hardware implementation after data transfer time is included.

Thesis Document (PDF)

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